I cannot directly provide or distribute copyrighted PDF files such as the PCI Express Base Specification Revision 6.0. That document is owned by PCI-SIG (Peripheral Component Interconnect Special Interest Group) and is only available to members who have signed a non-disclosure agreement.
| Feature | PCIe 5.0 (Gen 5) | PCIe 6.0 (Gen 6) | | :--- | :--- | :--- | | Data Rate | 32 GT/s | 64 GT/s | | Bandwidth (x16) | ~64 GB/s (approx. 128 GB/s bi-directional) | ~128 GB/s (approx. 256 GB/s bi-directional) | | Encoding Scheme | 128b/130b (NRZ) | PAM4 (with FEC) | | Packet Format | Variable size (TLP/ DLLP) | Fixed-size FLIT (256 bytes) | | Power Management | L1 substates | L0p (Per-lane power down) | | Target Latency | Standard | Sub-Ins latency (via FLIT) | pci express base specification revision 60 pdf
FLIT-Based Encoding: The specification adopts FLIT (Flow Control Unit) mode, where data is organized into fixed-size packets of 256 bytes. This structure is essential for implementing the new error correction mechanisms required by PAM4's higher noise sensitivity. I cannot directly provide or distribute copyrighted PDF
Previous generations (PCIe 1.0 through 5.0) utilized NRZ signaling, which encodes one bit of data per clock cycle (high voltage = 1, low voltage = 0). However, as frequencies increase to 64 GT/s, the bit time becomes too short for traditional NRZ to maintain signal integrity over standard PCB traces. To maintain bandwidth without lengthening the channel, the specification adopted PAM-4. PCIe 6
Every FLIT contains its own error correction bits. The lightweight Forward Error Correction (FEC) working alongside a robust Cyclic Redundancy Check (CRC) ensures that errors are corrected instantly at the physical layer without requiring a time-consuming replay of the data. This keeps latency incredibly low, which is vital for AI workloads. How to Access the PCIe 6.0 Specification PDF